数字集成电路物理设计阶段寄生提取与时延计算 Alternative Title Parasitic Extraction and Timing Calculation of Digital Integrated Circuit for Physical Design Stage 公维冰 Thesis Advisor 周宇斌 2010-05-29 Degree Grantor 兰州大学 Place of Conferral 兰州 Degree Name 硕士 Keyword 寄生提取 时延计算 Steiner树 Congestion信息 Elmore算法 Abstract 当前大规模集成电路工艺已经逐渐从深亚微米向纳米级发展，线网寄生参数提取已经变成集成电路中延迟计算过程中不可忽略的组成部分。在大规模集成电路设计的版图布局和布线过程中，需要通过对电路的时延分析来对两个过程的结果提供指导，本文研究了布线前和 布线后的寄生参数提取和时延计算。 为了在布线前更快的时延分析，本文发展了一个基于两维电容库查找表方法的布线前寄生参数提取方法。这个方法生成虚拟布线和使用标准单元布局后的信息来估计拥塞信息，然后使用模式库方法来提取互连线上的寄生参数。这里通过改进的FLUTE 算法来生成寄生网络上的RC 树，线网上的线段的寄生电容通过布局后的拥塞信息来计算。通过对工业例子的测试，证明了此方法有很快的运算速度，并且与商业寄生提取工具有相同的计算精度。 本文研究了布线之后的寄生参数提取和时延计算。由于已经有了各个金属层的布线信息，只要根据实际的线网拓扑结构及信号的传输方向就可以直接进行寄生提取了。本文使用2.5 维电容计算模式，依据工艺文件建立电容数据库，然后根据电路中的环境给出电容模式拟合公式，得到每一段基本导线寄生提取单元的单位长度电容。 Other Abstract Currently with the technology scaling, the parasitic parameters of the interconnects have become dominant influencing the performance of VLSI circuits. For effective placement and route of VLSI circuits, parasitic extraction and timing analysis with high precision are required to provide guidance for them. In this thesis parasitic extraction and timing calculation respectively in pre-route and post- route stage are investigated. For faster timing closure, a parasitic extraction method is developed based on 2D pattern-library method for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction of route segment considering congestion are presented. Experiments are carried out on industrial design cases, whose results show that the proposed method has high computational speed and comparable accuracy as commercial tool. Parasitic extraction and timing calculation for post-route are investigated in this thesis. Ac- cording to real routing topology and signal transmitting direction, we can implement the parasitic extraction and timing calculation. With 2.5D capacitance pattern, the capacitance pattern database is created. The unit length parasitic capacitance of wire segment is obtained with the fitting formula produced using the capacitance database. URL 查看原文 Language 中文 Document Type 学位论文 Identifier https://ir.lzu.edu.cn/handle/262010/224687 Collection 数学与统计学院 Recommended CitationGB/T 7714 公维冰. 数字集成电路物理设计阶段寄生提取与时延计算[D]. 兰州. 兰州大学,2010.
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