兰州大学机构库 >数学与统计学院
集成电路规划布局设计方法研究
Alternative TitleResearch on Floorplan in VLSI Physical Design
常宝方
Thesis Advisor李廉
2011-05-24
Degree Grantor兰州大学
Place of Conferral兰州
Degree Name博士
Keyword大规模集成电路 物理设计 规划布局 平面式 分层式/多层次设计
Abstract布局规划是集成电路设计中的重要环节,对电路在芯片上的位置和电路模块之间的连线有重要影响。随着IC制造技术的进步,芯片单位面积上的电路密度愈高,因此电路设计的复杂度愈大,对布局规划设计也提出了很大的挑战。在本文中首先通过对IAR策略的改进提出了快速的平面式规划布局方法,在布局每一次的优化迭代过程中,选择移除影响当前规划布局的关键模块,并为该模块选择安置位置从而形成一个新布局,在对新位置进行评估时,通过新提出的评估方法减少了对无效解的评估,提升了规划布局的质量。与目前最好的平面式规划方法IARFP相比,在规 划布局的运行时间、总绕线长度及成功率等多个方面有明显提升。 同时,为应对电路设计中IP知识产权核,宏模块以及ASIC的广泛应用而提出的挑战,我们通过采用分层式(多层次)的设计方法降低设计的复杂度,在分层式设计中首先将电路划分为多个分组,每个分组仅包含限定数目的电路模块,在各个分组内进行独立的布局规划,使每个分组成为一个相对对立的整体,并以每个分组整体作为单元逐级合并形成一个完整布局,在分组内的合并采用基于平面式规划的快速布局方法使每个分组形成一个相对对立的整体,而在以分组整体为计算单元逐级的合并中提出了一种新的双层计算模式应对在逐级合并中白空间的累积效应。本文中 提到的分层式规划设计方法,MFIAR-SP,与目前最好的分层式规划方法DeFer相比,在关系芯片性能的总绕线长度等多个方面明显胜出。
Other AbstractFloorplanning is a very crucial step in modern VLSI designs. It dominates the top-level spatial structure of a chip and initially optimizes the interconnections. Thus a good floorplan solution among circuit modules definitely has a positive impact on the placement, routing and even manufacturing. In this paper, we propose an efficient approach for the evaluation of the insertion points. The proposed method evaluates 2n insertion points, instead of all (n + 1) 2<上标!> insertion points as did in the state-of-the-art. The proposed techniques can be integrated into the general simulated annealing algorithm, resulting in a fast algorithm for floorplanning. Experimental results show that, the state-of-the-art can be improved up to 37% in terms of running time, without loss of success rate. In addition, our algorithm is comparable to the state-of-the-art in terms of wirelength. Multilevel strategy is one of the most popular methods for fixed outline floorplanning. It partitions an original circuit into some sub-circuits and then merges them into relatively big ones. In this paper, we propose a novel evaluation approach and integrate it into the simulated annealing framework in the merging stage. Moreover, a novel search technique, which can almost keep away from the local optimal, is proposed to obtain better floorplans. Experimental results show that our approach can obtain better performance than the state-of-the-art in terms of runtime, wirelength and success rate.
URL查看原文
Language中文
Document Type学位论文
Identifierhttps://ir.lzu.edu.cn/handle/262010/225063
Collection数学与统计学院
Recommended Citation
GB/T 7714
常宝方. 集成电路规划布局设计方法研究[D]. 兰州. 兰州大学,2011.
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