兰州大学机构库 >物理科学与技术学院
无晶振快速锁定锁相环设计
Alternative TitleDesign of Quick Lock Non-Oscillator Phase Locked Loop
耿晓勇
Thesis Advisor杨建红
2013-05-29
Degree Grantor兰州大学
Place of Conferral兰州
Degree Name硕士
Keyword无晶振 电荷泵 数字跟踪分频器 基准振荡器 压控振荡器 鉴频鉴相器 低通滤波器
Abstract锁相环(Phase-Locked Loop, PLL)是一种使输入参考信号与输出信号在相位和频率完全一致的同步电路。随着电子技术的突飞猛进,集成CMOS锁相环得到了大量的应用。从消费电子产品到仪器仪表,从微处理器到大型的移动通信设备随处可见CMOS锁相环的身影。由于锁相环的广泛应用,锁相环技术一直是学术界研究的焦点之一。 本论文设计一种无基准锁相环,即无晶振可快速锁定的高精度电荷泵锁相环,其中包括基准振荡器、压控振荡器(VCO)、电荷泵(CP)、低通滤波器(LPF)、鉴频鉴相器(PFD)和数字跟踪分频器。模拟模块原理与经典结构相似,数字跟踪分频器模块则有其独特的功能:利用初始时PLL不精确时钟搜索系统中的同步信号,从中得到基准时钟并相应调整PLL的输出,这样只需一个主机基准信号就可精确锁定所需的时钟频率。 本设计采用了0.18μm CMOS工艺,数字和模拟模块分别采用了Spectre和ModelSim软件进行了仿真验证。在外部系统基准时钟采用0.5KHz的低频时钟的情况下,一个基准过后300µs左右时间内该锁相环系统就达到了稳定的状态,而普通的模拟锁相环在这种应用环境下需要数个基准时钟周期,即需数毫秒到数十毫秒的时间才能完成锁定工作。该设计实现了锁相环的快速锁定,在提高应用便捷性的同时也提高了电路的可靠性,达到了预期的效果。
Other AbstractThe Phase-Locked Loop (PLL) is synchronizing circuit which can make the input reference signal exactly consist with the output signal in phase and frequency. With the rapid development of electronic technology, the integrated CMOS PLL has been a large number of applications. The shadow of the CMOS PLL can be seen everywhere from the consumption of electronics to the instrumentations, from the microprocessors to the large-scale mobile communication devices. Due to the extensive application of the PLL, the PLL has been the focus of academic research. In this context, The Non-oscillator PLL was designed, that is the precision charge pump PLL of non-oscillator, including the reference oscillator, the voltage controlled oscillator (VCO), the charge pump (CP), the low-pass filter (LPF), the phase frequency detector (PFD) and digital tracking divider. The analog module similarity with classical architecture, the digital tracking divider module has its own unique features: the use of the initial PLL inaccurate clock search system synchronization signal, obtaining the reference clock and a corresponding adjustment to the output of the PLL, so that only one host reference signal can pinpoint the desired clock frequency. In this paper, a 0.18 μm CMOS process were applied, the digital circuits modules and the analog circuits modules were used Spectre and ModelSim software to simulate and verify separately, and then emulate the whole system. When the external system reference clock were used a low-frequency clock (0.5KHz), the PPL system were achieved a steady state after a reference (about 300μs). But the ordinary analog PPL requires a number of reference clock cycles in this environment, it will take a few milliseconds to tens of milliseconds to complete lock. The mixed analog-digital PPL achieved a fast locking of PPL, improved the application convenience while also improved the reliability of the circuit to achieve the desired results.
URL查看原文
Language中文
Document Type学位论文
Identifierhttps://ir.lzu.edu.cn/handle/262010/229216
Collection物理科学与技术学院
Recommended Citation
GB/T 7714
耿晓勇. 无晶振快速锁定锁相环设计[D]. 兰州. 兰州大学,2013.
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